[PATCH] D103211: [RISCV] Improve register allocation for masked vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: frasercrmck, evandro, HsiangKai, rogfer01, khchen, arcbbb.
Herald added subscribers: StephenFan, vkmr, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
craig.topper requested review of this revision.
Herald added a subscriber: MaskRay.
Herald added a project: LLVM.

The first source has the same EEW as the destination, but we're
using earlyclobber which prevents them from ever being the same
register.

To workaround this, add a special TIED pseudo to use whenever the
first source and merge operand are the same value. This allows
us to use a single operand for the merge operand and first source
which we can then tie to the destination. A tied source disables
earlyclobber for that operand.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103211

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll

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