[PATCH] D103291: [AArch64][GISel] and+or+shl => bfi

Jessica Paquette via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri May 28 12:26:38 PDT 2021


paquette added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/GlobalISel/select-bitfield-insert.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -o - -verify-machineinstrs -global-isel | FileCheck %s --check-prefixes=CHECK,GISEL
----------------
jroelofs wrote:
> paquette wrote:
> > Is it possible to use a MIR testcase instead?
> IIUC, a MIR test case wouldn't show that we're doing as well as (and in some cases better than) SDAG, but I'm happy to convert it if you think that doesn't matter so much.
Ah, okay, I see. I think it's fine either way.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103291/new/

https://reviews.llvm.org/D103291



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