[PATCH] D103280: [SDAG] try harder to fold casts into vector compare

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:10908
     SDValue N01 = N0.getOperand(1);
     ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
     EVT N00VT = N00.getValueType();
----------------
You already have `CC`


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:10946-10947
+          TLI.isOperationLegalOrCustom(ISD::SETCC, VT) &&
+          !TLI.isOperationLegalOrCustom(ISD::SETCC, SVT)) {
+        // We have an unsupported narrow vector compare op that would be legal
+        // if extended to the destination type. See if the compare operands
----------------
`SVT` is the result type of comparison of values with `N00VT` type.
Shouldn't this be `!TLI.isOperationLegalOrCustom(ISD::SETCC, N00VT)` ?


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:10950
+        // can be freely extended to the destination type.
+        SDValue Op0 = N0.getOperand(0), Op1 = N0.getOperand(1);
+        auto isFreeToZext = [&](SDValue V) {
----------------
You already have `N00` and `N01`


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:10958
+          // TODO: Handle more than one use if the other uses are free to zext.
+          return ISD::isNON_EXTLoad(V.getNode()) &&
+                 ISD::isUNINDEXEDLoad(V.getNode()) &&
----------------
I think we can also accept `ZEXTLOAD`, since we'd just increase the desired number of leading zeros?


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  https://reviews.llvm.org/D103280/new/

https://reviews.llvm.org/D103280