[PATCH] D102422: [RISCV] Allow passing fixed-length vectors via the stack

Fraser Cormack via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu May 27 06:22:19 PDT 2021


This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8c73a31c1175: [RISCV] Allow passing fixed-length vectors via the stack (authored by frasercrmck).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102422/new/

https://reviews.llvm.org/D102422

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
  llvm/test/CodeGen/RISCV/rvv/unsupported-calling-conv.ll

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