[PATCH] D102422: [RISCV] Allow passing fixed-length vectors via the stack

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck updated this revision to Diff 348192.
frasercrmck added a comment.

- rebase on top of test changes
- simpler way of expressing alignment


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102422/new/

https://reviews.llvm.org/D102422

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
  llvm/test/CodeGen/RISCV/rvv/unsupported-calling-conv.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D102422.348192.patch
Type: text/x-patch
Size: 20596 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210527/f647f4a8/attachment.bin>