[PATCH] D102739: [RISCV] Enable cross basic block aware vsetvli insertion

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.

LGTM.



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Comment at: llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll:86
+
+; FIXME: The last vsetvli is redundant, but we need to look through a phi to
+; prove it.
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Interesting. I was kinda hoping the middle-end would hoist it, but I guess that's not possible because the intrinsic is marked as having side effects. I looked at that a while ago when a vsetvli intrinsic was preventing two identical loads on either side being merged, and was wondering if we might something less nuclear than `IntrHasSideEffects`, because that seems to negate `IntrNoMem` in useful optimizations.


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https://reviews.llvm.org/D102739