[llvm] 63cc9fd - [MCA][InOrderIssueStage] Fix LastWriteBackCycle computation.
Andrea Di Biagio via llvm-commits
llvm-commits at lists.llvm.org
Wed May 26 06:19:08 PDT 2021
Author: Andrea Di Biagio
Date: 2021-05-26T14:17:43+01:00
New Revision: 63cc9fd579b20e225d1109ebd077a6a13c97c2ab
URL: https://github.com/llvm/llvm-project/commit/63cc9fd579b20e225d1109ebd077a6a13c97c2ab
DIFF: https://github.com/llvm/llvm-project/commit/63cc9fd579b20e225d1109ebd077a6a13c97c2ab.diff
LOG: [MCA][InOrderIssueStage] Fix LastWriteBackCycle computation.
Conservatively use the instruction latency to compute the last write-back cycle.
Before this patch, the last write cycle computation was incorrect for store
instructions that didn't declare any register writes.
Added:
Modified:
llvm/lib/MCA/Stages/InOrderIssueStage.cpp
llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-stats.s
llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-views.s
Removed:
################################################################################
diff --git a/llvm/lib/MCA/Stages/InOrderIssueStage.cpp b/llvm/lib/MCA/Stages/InOrderIssueStage.cpp
index a32319b4b3901..273685234c85b 100644
--- a/llvm/lib/MCA/Stages/InOrderIssueStage.cpp
+++ b/llvm/lib/MCA/Stages/InOrderIssueStage.cpp
@@ -61,21 +61,8 @@ static bool hasResourceHazard(const ResourceManager &RM, const InstRef &IR) {
return false;
}
-static unsigned findLastWriteBackCycle(const InstRef &IR) {
- unsigned LastWBCycle = 0;
- for (const WriteState &WS : IR.getInstruction()->getDefs()) {
- int CyclesLeft = WS.getCyclesLeft();
- if (CyclesLeft == UNKNOWN_CYCLES)
- CyclesLeft = WS.getLatency();
- if (CyclesLeft < 0)
- CyclesLeft = 0;
- LastWBCycle = std::max(LastWBCycle, (unsigned)CyclesLeft);
- }
- return LastWBCycle;
-}
-
static unsigned findFirstWriteBackCycle(const InstRef &IR) {
- unsigned FirstWBCycle = ~0U;
+ unsigned FirstWBCycle = IR.getInstruction()->getLatency();
for (const WriteState &WS : IR.getInstruction()->getDefs()) {
int CyclesLeft = WS.getCyclesLeft();
if (CyclesLeft == UNKNOWN_CYCLES)
@@ -266,7 +253,7 @@ llvm::Error InOrderIssueStage::tryIssue(InstRef &IR, unsigned *StallCycles) {
IssuedInst.push_back(IR);
if (!IR.getInstruction()->getDesc().RetireOOO)
- LastWriteBackCycle = findLastWriteBackCycle(IR);
+ LastWriteBackCycle = IS.getCyclesLeft();
return llvm::ErrorSuccess();
}
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-stats.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-stats.s
index 9081fb525ee22..f5ce26e43b6ac 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-stats.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-stats.s
@@ -10,12 +10,12 @@ str w0, [x21, x18, lsl #2]
# CHECK: Iterations: 2
# CHECK-NEXT: Instructions: 12
-# CHECK-NEXT: Total Cycles: 20
+# CHECK-NEXT: Total Cycles: 23
# CHECK-NEXT: Total uOps: 14
# CHECK: Dispatch Width: 2
-# CHECK-NEXT: uOps Per Cycle: 0.70
-# CHECK-NEXT: IPC: 0.60
+# CHECK-NEXT: uOps Per Cycle: 0.61
+# CHECK-NEXT: IPC: 0.52
# CHECK-NEXT: Block RThroughput: 3.5
# CHECK: Instruction Info:
@@ -35,7 +35,7 @@ str w0, [x21, x18, lsl #2]
# CHECK-NEXT: 1 4 1.00 * str w0, [x21, x18, lsl #2]
# CHECK: Dynamic Dispatch Stall Cycles:
-# CHECK-NEXT: RAT - Register unavailable: 8 (40.0%)
+# CHECK-NEXT: RAT - Register unavailable: 8 (34.8%)
# CHECK-NEXT: RCU - Retire tokens unavailable: 0
# CHECK-NEXT: SCHEDQ - Scheduler full: 0
# CHECK-NEXT: LQ - Load queue full: 0
@@ -44,15 +44,15 @@ str w0, [x21, x18, lsl #2]
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT: 0, 10 (50.0%)
-# CHECK-NEXT: 1, 6 (30.0%)
-# CHECK-NEXT: 2, 4 (20.0%)
+# CHECK-NEXT: 0, 13 (56.5%)
+# CHECK-NEXT: 1, 6 (26.1%)
+# CHECK-NEXT: 2, 4 (17.4%)
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
# CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT: 0, 10 (50.0%)
-# CHECK-NEXT: 1, 6 (30.0%)
-# CHECK-NEXT: 2, 4 (20.0%)
+# CHECK-NEXT: 0, 13 (56.5%)
+# CHECK-NEXT: 1, 6 (26.1%)
+# CHECK-NEXT: 2, 4 (17.4%)
# CHECK: Scheduler's queue usage:
# CHECK-NEXT: No scheduler resources used.
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-views.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-views.s
index d49e68adc1c3f..a8bddbbd4a3b6 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-views.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-views.s
@@ -10,12 +10,12 @@ str w0, [x21, x18, lsl #2]
# CHECK: Iterations: 2
# CHECK-NEXT: Instructions: 12
-# CHECK-NEXT: Total Cycles: 20
+# CHECK-NEXT: Total Cycles: 23
# CHECK-NEXT: Total uOps: 14
# CHECK: Dispatch Width: 2
-# CHECK-NEXT: uOps Per Cycle: 0.70
-# CHECK-NEXT: IPC: 0.60
+# CHECK-NEXT: uOps Per Cycle: 0.61
+# CHECK-NEXT: IPC: 0.52
# CHECK-NEXT: Block RThroughput: 3.5
# CHECK: Instruction Info:
@@ -35,7 +35,7 @@ str w0, [x21, x18, lsl #2]
# CHECK-NEXT: 1 4 1.00 * str w0, [x21, x18, lsl #2]
# CHECK: Dynamic Dispatch Stall Cycles:
-# CHECK-NEXT: RAT - Register unavailable: 8 (40.0%)
+# CHECK-NEXT: RAT - Register unavailable: 8 (34.8%)
# CHECK-NEXT: RCU - Retire tokens unavailable: 0
# CHECK-NEXT: SCHEDQ - Scheduler full: 0
# CHECK-NEXT: LQ - Load queue full: 0
@@ -44,15 +44,15 @@ str w0, [x21, x18, lsl #2]
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT: 0, 10 (50.0%)
-# CHECK-NEXT: 1, 6 (30.0%)
-# CHECK-NEXT: 2, 4 (20.0%)
+# CHECK-NEXT: 0, 13 (56.5%)
+# CHECK-NEXT: 1, 6 (26.1%)
+# CHECK-NEXT: 2, 4 (17.4%)
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
# CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT: 0, 10 (50.0%)
-# CHECK-NEXT: 1, 6 (30.0%)
-# CHECK-NEXT: 2, 4 (20.0%)
+# CHECK-NEXT: 0, 13 (56.5%)
+# CHECK-NEXT: 1, 6 (26.1%)
+# CHECK-NEXT: 2, 4 (17.4%)
# CHECK: Scheduler's queue usage:
# CHECK-NEXT: No scheduler resources used.
@@ -90,20 +90,20 @@ str w0, [x21, x18, lsl #2]
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
-# CHECK-NEXT: Index 0123456789
-
-# CHECK: [0,0] DeeE . . . . ldr w4, [x2], #4
-# CHECK-NEXT: [0,1] .DeeE. . . . ldr w5, [x3]
-# CHECK-NEXT: [0,2] . DeeeE . . . madd w0, w5, w4, w0
-# CHECK-NEXT: [0,3] . DeeE . . . add x3, x3, x13
-# CHECK-NEXT: [0,4] . DeeE . . . subs x1, x1, #1
-# CHECK-NEXT: [0,5] . . DeeeE . . str w0, [x21, x18, lsl #2]
-# CHECK-NEXT: [1,0] . . DeeE . . ldr w4, [x2], #4
-# CHECK-NEXT: [1,1] . . DeeE . . ldr w5, [x3]
-# CHECK-NEXT: [1,2] . . . DeeeE . madd w0, w5, w4, w0
-# CHECK-NEXT: [1,3] . . . DeeE . add x3, x3, x13
-# CHECK-NEXT: [1,4] . . . DeeE . subs x1, x1, #1
-# CHECK-NEXT: [1,5] . . . DeeeE str w0, [x21, x18, lsl #2]
+# CHECK-NEXT: Index 0123456789 012
+
+# CHECK: [0,0] DeeE . . . . . ldr w4, [x2], #4
+# CHECK-NEXT: [0,1] .DeeE. . . . . ldr w5, [x3]
+# CHECK-NEXT: [0,2] . DeeeE . . . . madd w0, w5, w4, w0
+# CHECK-NEXT: [0,3] . DeeE . . . . add x3, x3, x13
+# CHECK-NEXT: [0,4] . DeeE . . . . subs x1, x1, #1
+# CHECK-NEXT: [0,5] . . DeeeE . . . str w0, [x21, x18, lsl #2]
+# CHECK-NEXT: [1,0] . . .DeeE. . . ldr w4, [x2], #4
+# CHECK-NEXT: [1,1] . . . DeeE . . ldr w5, [x3]
+# CHECK-NEXT: [1,2] . . . DeeeE. . madd w0, w5, w4, w0
+# CHECK-NEXT: [1,3] . . . .DeeE. . add x3, x3, x13
+# CHECK-NEXT: [1,4] . . . .DeeE. . subs x1, x1, #1
+# CHECK-NEXT: [1,5] . . . . DeeeE str w0, [x21, x18, lsl #2]
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
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