[llvm] 8be23ed - [SLP][NFC]Add a test for multiple uses of insertelement instruction,

[Alexey Bataev via llvm-commits]

Author: Alexey Bataev
Date: 2021-05-26T06:17:03-07:00
New Revision: 8be23ed3f02ae633193c400909d135876de6c8cb

URL: https://github.com/llvm/llvm-project/commit/8be23ed3f02ae633193c400909d135876de6c8cb
DIFF: https://github.com/llvm/llvm-project/commit/8be23ed3f02ae633193c400909d135876de6c8cb.diff

LOG: [SLP][NFC]Add a test for multiple uses of insertelement instruction,
NFC.

Added: 
    llvm/test/Transforms/SLPVectorizer/X86/insert-element-multiple-uses.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/SLPVectorizer/X86/insert-element-multiple-uses.ll b/llvm/test/Transforms/SLPVectorizer/X86/insert-element-multiple-uses.ll
new file mode 100644
index 0000000000000..713e0dad5ee2b
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/insert-element-multiple-uses.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -slp-vectorizer < %s | FileCheck %s
+
+define void @main() {
+; CHECK-LABEL: @main(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* undef, align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i64> [[TMP0]], <i64 1, i64 1>
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0
+; CHECK-NEXT:    [[CMP_I:%.*]] = icmp eq i64 [[TMP2]], 0
+; CHECK-NEXT:    [[VEC_0_I:%.*]] = select i1 [[CMP_I]], <2 x i64> [[TMP1]], <2 x i64> [[TMP1]]
+; CHECK-NEXT:    ret void
+;
+entry:
+  %0 = load <2 x i64>, <2 x i64>* undef, align 16
+  %vec.0.vec.extract.i = extractelement <2 x i64> %0, i32 0
+  %add.i = add i64 %vec.0.vec.extract.i, 1
+  %vec.0.vec.insert.i = insertelement <2 x i64> %0, i64 %add.i, i32 0
+  %cmp.i = icmp eq i64 %add.i, 0
+  %vec.8.vec.extract.i = extractelement <2 x i64> %0, i32 1
+  %inc.i = add i64 %vec.8.vec.extract.i, 1
+  %vec.8.vec.insert.i = insertelement <2 x i64> %vec.0.vec.insert.i, i64 %inc.i, i32 1
+  %vec.0.i = select i1 %cmp.i, <2 x i64> %vec.8.vec.insert.i, <2 x i64> %vec.0.vec.insert.i
+  ret void
+}
+