[PATCH] D99355: Implementation of intrinsic and SDNode definitions for VP load, store, gather, scatter.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

I had a thought about alignment. Do we have a plan on how to deal with unaligned accesses? The other non-VP masked intrinsics are scalarized by the `ScalarizeMaskedMemIntrin` pass and regular loads and stores are handled by -- I believe -- `LegalizeDAG`.

This doesn't apply for scalable vectors, where presumably the onus is on the author/compiler transform not to emit them in the first place. But then for that we have TTI methods like `isLegalMaskedStore` and friends.


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  https://reviews.llvm.org/D99355/new/

https://reviews.llvm.org/D99355