[PATCH] D103010: [PowerPC] Export 16 byte load-store instructions

[Kai Luo via Phabricator via llvm-commits]

lkail added a comment.

> we do have to devise a way to ensure RA doesn't allocate the same register to the base and result of LQ

One way I can figure out now is to have an additional pseudo instruction after `LQ` which uses the base register of `LQ` so that the live range of base register and result register overlap.


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https://reviews.llvm.org/D103010