[PATCH] D103010: [PowerPC] Export 16 byte load-store instructions

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added a comment.

Although I am obviously not opposed to adding these instructions and the necessary register classes, we do have to devise a way to ensure RA doesn't allocate the same register to the base and result of `LQ`. An additional complication for this check is ensuring that if `RA == 0`, `RTp != 0`.



================
Comment at: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:118
+  // Quadword load and store.
+  ImmToIdxMap[PPC::LQ] = PPC::LQ;
+  ImmToIdxMap[PPC::STQ] = PPC::STQ;
----------------
This is likely problematic. What happens if we need to spill one of these at an offset from the stack pointer that doesn't fit in a DQ field? I imagine something breaks. These have to be handled differently in that we need to bump the base register rather than loading an immediate into a register and using it as an index.
See `PPCRegisterInfo::eliminateFrameIndex()`


================
Comment at: llvm/lib/Target/PowerPC/PPCRegisterInfo.td:23
 def sub_pair1 : SubRegIndex<256, 256>;
+def sub_gp8_pair0 : SubRegIndex<64>;
+def sub_gp8_pair1 : SubRegIndex<64, 64>;
----------------
These names are odd, they seem to suggest that there are pairs that are subregisters, but it is actually the individual registers. Maybe:
```
sub_gp8_x0
sub_gp8_x1
```


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  https://reviews.llvm.org/D103010/new/

https://reviews.llvm.org/D103010