[PATCH] D98240: [VectorCombine] Simplify to scalar store if only one element updated

[Hendrik Greving via Phabricator via llvm-commits]

hgreving added a comment.

For targets not supporting scalar load from vector memory (like ours), this breaks it:

%43 = load <8 x i32>, <8 x i32> addrspace(201)* %1, align 32, !tbaa !28

  %44 = extractelement <8 x i32> %43, i32 0

Now:

%43 = getelementptr inbounds <8 x i32>, <8 x i32> addrspace(201)* %1, i32 0, i32 0

  %44 = load i32, i32 addrspace(201)* %43, align 32

Are targets expected to provide patterns?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D98240/new/

https://reviews.llvm.org/D98240