[PATCH] D103126: [RISCV] Don't propagate VL/VTYPE across inline assembly in the Insert VSETVLI pass.

[Craig Topper via Phabricator via llvm-commits]

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It's conceivable someone could put a vsetvli in inline assembly
so its safer to consider them as barriers. The alternative would
be to trust that the user marks VL and VTYPE registers as clobbers
of the inline assembly if they do that, but hat seems error prone.

I'm assuming inline assembly in vector code is going to be rare.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103126

Files:
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir

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