[PATCH] D102526: [AMDGPU] Set unused dst_sel to '?' in the encoding

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGf4c0fdc6c9db: [AMDGPU] Set unused dst_sel to '?' in the encoding (authored by rampitec).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102526/new/

https://reviews.llvm.org/D102526

Files:
  llvm/lib/Target/AMDGPU/VOPInstructions.td
  llvm/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt
  llvm/test/MC/Disassembler/AMDGPU/sdwa_vi.txt


Index: llvm/test/MC/Disassembler/AMDGPU/sdwa_vi.txt
===================================================================
--- llvm/test/MC/Disassembler/AMDGPU/sdwa_vi.txt
+++ llvm/test/MC/Disassembler/AMDGPU/sdwa_vi.txt
@@ -368,3 +368,9 @@
 
 # VI: v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x00,0x06,0x06]
 0xf9,0x04,0x0a,0x00,0x01,0x00,0x06,0x06
+
+# VI: v_cmp_lt_f32 vcc, v2, v4 src0_sel:BYTE_1 src1_sel:DWORD ; encoding: [0xf9,0x08,0x82,0x7c,0x02,0x00,0x01,0x06]
+0xf9,0x08,0x82,0x7c,0x02,0x00,0x01,0x06
+
+# VI: v_cmp_lt_f32 vcc, v2, v4 src0_sel:BYTE_1 src1_sel:DWORD ; encoding: [0xf9,0x08,0x82,0x7c,0x02,0x00,0x01,0x06]
+0xf9,0x08,0x82,0x7c,0x02,0x06,0x01,0x06
Index: llvm/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt
===================================================================
--- llvm/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt
+++ llvm/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt
@@ -448,6 +448,12 @@
 # GFX9: v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x02,0x04]
 0xf9 0x04 0x22 0x7c 0x01 0x00 0x02 0x04
 
+# GFX9: v_cmp_lt_f32_sdwa vcc, v2, v4 src0_sel:BYTE_1 src1_sel:DWORD ; encoding: [0xf9,0x08,0x82,0x7c,0x02,0x00,0x01,0x06]
+0xf9,0x08,0x82,0x7c,0x02,0x00,0x01,0x06
+
+# GFX9: v_cmp_lt_f32_sdwa vcc, v2, v4 src0_sel:BYTE_1 src1_sel:DWORD ; encoding: [0xf9,0x08,0x82,0x7c,0x02,0x00,0x01,0x06]
+0xf9,0x08,0x82,0x7c,0x02,0x06,0x01,0x06
+
 #-----------------------------------------------------------------------------#
 # Modifiers
 #-----------------------------------------------------------------------------#
Index: llvm/lib/Target/AMDGPU/VOPInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -417,8 +417,8 @@
   bits<1> clamp;
 
   let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
-  let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, 0);
-  let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, 0);
+  let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, ?);
+  let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, ?);
   let Inst{45}    = !if(P.HasSDWAClamp, clamp{0}, 0);
   let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0);
   let Inst{51}    = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0);
@@ -468,8 +468,8 @@
   bits<1> clamp;
   bits<2> omod;
 
-  let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, 0);
-  let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, 0);
+  let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, ?);
+  let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, ?);
   let Inst{45}    = !if(P.HasSDWAClamp, clamp{0}, 0);
   let Inst{47-46} = !if(P.HasSDWAOMod, omod{1-0}, 0);
 }


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