[PATCH] D102925: [RISCV] Add wrong arch attribute objfile test.

[Zakk Chen via Phabricator via llvm-commits]

khchen updated this revision to Diff 347280.
khchen added a comment.

update test to show asm has F instructions.

This patch is going to fix wrong attribute for a standalone function or
all functions have same target feature when -march string is missing.

But I feel that you are talking about another problem,
something like how to handle different target feature in the same compilation unit or in
different compilation units. This is not what I want to fix.

Do you still feel this fixed is redundant?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102925/new/

https://reviews.llvm.org/D102925

Files:
  llvm/test/CodeGen/RISCV/subtarget-features-obj-bug.ll


Index: llvm/test/CodeGen/RISCV/subtarget-features-obj-bug.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/subtarget-features-obj-bug.ll
@@ -0,0 +1,19 @@
+; RUN: llc -o - < %s | FileCheck %s
+; RUN: llc --filetype=obj -o - < %s | llvm-readelf -A - \
+; RUN:   | FileCheck %s -check-prefix=ATTRIBUTE
+
+; ATTRIBUTE: TagName: arch
+; ATTRIBUTE: Value: rv64i2p0
+
+target triple = "riscv64-unknown-linux-gnu"
+
+; ASM includes F standard extension instructions but arch attribute information is only RV64I base instructions
+
+define float @foo1(i32 %a) nounwind #0 {
+; CHECK: fcvt.s.w        ft0, a0
+; CHECK: fmv.x.w a0, ft0
+  %conv = sitofp i32 %a to float
+  ret float %conv
+}
+
+attributes #0 = { "target-features"="+64bit,+a,+c,+d,+f,+m"}


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