[PATCH] D102737: [RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.

[ShihPo Hung via Phabricator via llvm-commits]

arcbbb added a comment.

LGTM



================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:301
+    Register AVLReg = MI.getOperand(1).getReg();
+    assert((AVLReg != RISCV::X0 || MI.getOperand(0).getReg() != RISCV::X0) &&
+           "Can't handle X0, X0 vsetvli yet");
----------------
arcbbb wrote:
> is the assertion avoidable by doing `setAVLReg(RISCV::NoRegister)` for vtype-only change,  and something like
> `BBInfo.change = Merge(BBInfo.change, getInfoForVSETVLI)` to keep the latest VL & vtype change ?
Sorry I forgot it was not possible because vsetvli wasn't inserted at this stage. Please ignore it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102737/new/

https://reviews.llvm.org/D102737