[PATCH] D102739: [RISCV] Enable cross basic block aware vsetvli insertion

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 346919.
craig.topper added a comment.

Add phase 1 and 2 on top of phase 3 with all insertion done in phase 3.

This makes phase 1 and phase 3 look very similar since we still need to
determine the basic block's effect even if we don't insert anything.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102739/new/

https://reviews.llvm.org/D102739

Files:
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D102739.346919.patch
Type: text/x-patch
Size: 125490 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210521/8faae7a0/attachment.bin>