[PATCH] D102854: [RISCV][test] Add new tests of or/xor in the zbs extension

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rv32zbs.ll:801
 
+; This should not be optimized since bit 12 of 6145 is set.
+define i32 @xor_i32_6145(i32 %a) nounwind {
----------------
craig.topper wrote:
> benshi001 wrote:
> > jrtc27 wrote:
> > > Everything should always be optimised, but you mean a specific optimisation doesn't apply
> > This patch will show how
> > ```
> > lui r1, xxx
> > addi r1, r1, yyy
> > or r0, r0, r1
> > ```
> > 
> > will be optimized to
> > ```
> > ori r0, r0, zzz
> > bseti r0, 11
> > bseti r0, hi
> > ```
> > 
> > An extra register is saved.
> I think @jrtc27 means the comment should be understandable by someone in the future without needing to know about a specific patch/commit.
Yes, the comment is complete nonsense when you read the file, it only makes some amount of sense when looking specifically at this diff, but even then is not the best way to express that.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102854/new/

https://reviews.llvm.org/D102854