[PATCH] D102854: [RISCV][test] Add new tests of or/xor in the zbs extension

[Ben Shi via Phabricator via llvm-commits]

benshi001 marked an inline comment as done.
benshi001 added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rv32zbs.ll:801
 
+; This should not be optimized since bit 12 of 6145 is set.
+define i32 @xor_i32_6145(i32 %a) nounwind {
----------------
jrtc27 wrote:
> Everything should always be optimised, but you mean a specific optimisation doesn't apply
This patch will show how
```
lui r1, xxx
addi r1, r1, yyy
or r0, r0, r1
```

will be optimized to
```
ori r0, r0, zzz
bseti r0, 11
bseti r0, hi
```

An extra register is saved.


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  https://reviews.llvm.org/D102854/new/

https://reviews.llvm.org/D102854