[PATCH] D102737: [RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D102737#2770360 <https://reviews.llvm.org/D102737#2770360>, @rogfer01 wrote:

> This is looking great.
>
> I was wondering if we can delay all the insertions to phase 3. I understand this would require keep tracking the insertion points. I mention that because it could help if we want to be able to simplify further the insertion points after phase1 or phase2. In that setting, phase 1 could be named something like `computeDemandedVSETVL`, phase 2 could be `computeIncomingVLVTYPE` and then phase 3 `emitVSETVL`
>
> An example of possible optimization, could be a loop that loads SEW=32 vectors and does a widening operation (say `vfwmac`) and stores the resulting SEW=64 (without further processing that vector) using `vse64`. Looks to me we could just go with a single `vsetvl` here with SEW=32.
>
> What do you think?

I think we can still do that in phase 1. We could probably change the opcode of the store there as well. But I guess not if the store was the first instruction in the block.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102737/new/

https://reviews.llvm.org/D102737