[PATCH] D102759: [AArch64ISelDAGToDAG] Supplement cases for ORRWrs/ORRXrs when calculating usefulbits

[Tiehu Zhang via Phabricator via llvm-commits]

TiehuZhang updated this revision to Diff 346611.
TiehuZhang added a comment.

update the testcase


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102759/new/

https://reviews.llvm.org/D102759

Files:
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/test/CodeGen/AArch64/arm64-isel-or.ll


Index: llvm/test/CodeGen/AArch64/arm64-isel-or.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/arm64-isel-or.ll
@@ -0,0 +1,40 @@
+; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -stop-after=instruction-select -o - | FileCheck %s
+; ModuleID = '<stdin>'
+source_filename = "<stdin>"
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-unknown-linux-gnu"
+
+ at e = dso_local local_unnamed_addr global i32 0, align 4
+
+; CHECK-LABEL: name: main
+; CHECK-NOT: ORRWrs undef renamable $w8, undef renamable $w8, 73
+; Function Attrs: norecurse
+define dso_local i32 @main() local_unnamed_addr {
+entry:
+  %0 = load i32, i32* @e, align 4
+  %shr = lshr i32 %0, 9
+  %or = or i32 %shr, %0
+  %shr.1 = lshr i32 %or, 9
+  %or.1 = or i32 %shr.1, %or
+  %shr.2 = lshr i32 %or.1, 9
+  %or.2 = or i32 %shr.2, %or.1
+  %shr.3 = lshr i32 %or.2, 9
+  %or.3 = or i32 %shr.3, %or.2
+  %shr.4 = lshr i32 %or.3, 9
+  %or.4 = or i32 %shr.4, %or.3
+  %shr.5 = lshr i32 %or.4, 9
+  %or.5 = or i32 %shr.5, %or.4
+  %shr.6 = lshr i32 %or.5, 9
+  %or.6 = or i32 %shr.6, %or.5
+  %shr.7 = lshr i32 %or.6, 9
+  %or.7 = or i32 %shr.7, %or.6
+  %shr.8 = lshr i32 %or.7, 9
+  %or.8 = or i32 %shr.8, %or.7
+  %shr.9 = lshr i32 %or.8, 9
+  %or.9 = or i32 %shr.9, %or.8
+  %shr.10 = lshr i32 %or.9, 9
+  %or.10 = or i32 %shr.10, %or.9
+  store i32 %or.10, i32* @e, align 4
+  ret i32 0
+}
+
Index: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -2305,6 +2305,8 @@
   case AArch64::ORRXrs:
     if (UserNode->getOperand(1) != Orig)
       return;
+    if (UserNode->getOperand(0) == Orig)
+      return;
     return getUsefulBitsFromOrWithShiftedReg(SDValue(UserNode, 0), UsefulBits,
                                              Depth);
   case AArch64::BFMWri:


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