[PATCH] D102702: Experimental: inline assembly operands

Wed May 19 11:16:09 PDT 2021

jonpa marked 2 inline comments as done.
jonpa added inline comments.

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Comment at: llvm/lib/Target/X86/X86FloatingPoint.cpp:1549-1551
+      // its index and continue.  EXPERIMENTAL: This doesn't quite work since
+      // this is run after reg-alloc. Only virtual registers will have
+      // hasRegClassConstraint() currently, but there seems to be no good way
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pengfei wrote:
> Is this an existing bug for this pass, or affected by this patch? In which way, if it is affected?
No, it's not a current bug. This (and some other files) relies on the fact that currently the RegClass is only encoded for virtual registers... This patch is experimental in encoding the returned RegClass (from getRegForInlineAsmConstraint) always (also for physregs), and that's why some problems show up.

Thanks for taking a look... Have anybody else thought about this or would desire this?

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102702/new/

https://reviews.llvm.org/D102702