[PATCH] D102702: Experimental: inline assembly operands

Tue May 18 19:53:29 PDT 2021

pengfei added inline comments.

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Comment at: llvm/lib/Target/X86/X86FloatingPoint.cpp:1549-1551
+      // its index and continue.  EXPERIMENTAL: This doesn't quite work since
+      // this is run after reg-alloc. Only virtual registers will have
+      // hasRegClassConstraint() currently, but there seems to be no good way
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Is this an existing bug for this pass, or affected by this patch? In which way, if it is affected?

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Comment at: llvm/lib/Target/X86/X86FloatingPoint.cpp:1555
+      // Flags to indicate if the reg is originally virtual or physical..?
+      if (InlineAsm::hasRegClassConstraint(Flags, RCID) &&
+          (RCID == X86::RFP32RegClassID || RCID == X86::RFP64RegClassID ||
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So this can be removed?

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102702/new/

https://reviews.llvm.org/D102702