[PATCH] D102759: [AArch64ISelDAGToDAG] Supplement cases for ORRWrs/ORRXrs when calculating usefulbits

[Tiehu Zhang via Phabricator via llvm-commits]

TiehuZhang created this revision.
TiehuZhang added a reviewer: mdchen.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls.
TiehuZhang requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

For case,

      
  t8: i32 = or t7, t4
  t10: i32 = ORRWrs t8, t8, TargetConstant:i32<73>
      

the userfulbits of t8 should be full bits of itself (t8 | (t8 >> shiftConstant)). Current implementation doesn't catch the case and may get a wrong result. The patch supplements the missing case.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D102759

Files:
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/test/CodeGen/AArch64/arm64-isel-or.ll


Index: llvm/test/CodeGen/AArch64/arm64-isel-or.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/arm64-isel-or.ll
@@ -0,0 +1,71 @@
+; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -stop-after=instruction-select -o - | FileCheck %s
+; ModuleID = '<stdin>'
+source_filename = "<stdin>"
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-unknown-linux-gnu"
+
+ at d = dso_local local_unnamed_addr global i8 0, align 4
+ at e = dso_local local_unnamed_addr global i32 0, align 4
+ at f = dso_local local_unnamed_addr global i32 0, align 4
+ at .str = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 1
+
+; Function Attrs: norecurse nounwind readnone
+define dso_local i32 @_Z1aii(i32 %b, i32 %c) local_unnamed_addr {
+entry:
+  %tobool = icmp eq i32 %c, 0
+  br i1 %tobool, label %land.end.thread, label %land.end
+
+land.end:                                         ; preds = %entry
+  %div = sdiv i32 47483647, %c
+  %cmp = icmp slt i32 %div, %b
+  %spec.select = select i1 %cmp, i32 1, i32 %c
+  ret i32 %spec.select
+
+land.end.thread:                                  ; preds = %entry
+  ret i32 0
+}
+
+; CHECK-LABEL: name: main
+; CHECK-NOT: ORRWrs undef renamable $w8, undef renamable $w8, 73
+; Function Attrs: norecurse
+define dso_local i32 @main() local_unnamed_addr {
+entry:
+  %0 = load i32, i32* @e, align 4, !tbaa !1
+  %shr = lshr i32 %0, 9
+  %or = or i32 %shr, %0
+  %shr.1 = lshr i32 %or, 9
+  %or.1 = or i32 %shr.1, %or
+  %shr.2 = lshr i32 %or.1, 9
+  %or.2 = or i32 %shr.2, %or.1
+  %shr.3 = lshr i32 %or.2, 9
+  %or.3 = or i32 %shr.3, %or.2
+  %shr.4 = lshr i32 %or.3, 9
+  %or.4 = or i32 %shr.4, %or.3
+  %shr.5 = lshr i32 %or.4, 9
+  %or.5 = or i32 %shr.5, %or.4
+  %shr.6 = lshr i32 %or.5, 9
+  %or.6 = or i32 %shr.6, %or.5
+  %shr.7 = lshr i32 %or.6, 9
+  %or.7 = or i32 %shr.7, %or.6
+  %shr.8 = lshr i32 %or.7, 9
+  %or.8 = or i32 %shr.8, %or.7
+  %shr.9 = lshr i32 %or.8, 9
+  %or.9 = or i32 %shr.9, %or.8
+  %shr.10 = lshr i32 %or.9, 9
+  %or.10 = or i32 %shr.10, %or.9
+  store i32 %or.10, i32* @e, align 4, !tbaa !1
+  store i8 0, i8* @d, align 4, !tbaa !5
+  tail call void (...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32 %or.10)
+  ret i32 0
+}
+
+declare dso_local void @printf(...) local_unnamed_addr
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{!2, !2, i64 0}
+!2 = !{!"int", !3, i64 0}
+!3 = !{!"omnipotent char", !4, i64 0}
+!4 = !{!"Simple C++ TBAA"}
+!5 = !{!3, !3, i64 0}
Index: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -2305,6 +2305,8 @@
   case AArch64::ORRXrs:
     if (UserNode->getOperand(1) != Orig)
       return;
+    if (UserNode->getOperand(0) == Orig)
+      return;
     return getUsefulBitsFromOrWithShiftedReg(SDValue(UserNode, 0), UsefulBits,
                                              Depth);
   case AArch64::BFMWri:


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