[PATCH] D101834: [llvm][sve] Lowering for VLS MLOAD/MSTORE
Sander de Smalen via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed May 19 01:01:21 PDT 2021
sdesmalen added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17220
+
+ if (Load->getExtensionType() != ISD::LoadExtType::NON_EXTLOAD)
+ return SDValue();
----------------
Are you planning to handle sign/zero-extending loads in a follow-up patch?
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1184
+ // NEON doesn't support masked loads or stores, but SVE does
+ for (auto VT : {MVT::v4f16, MVT::v8f16, MVT::v2f32, MVT::v4f32, MVT::v1f64, MVT::v2f64,
+ MVT::v8i8, MVT::v16i8, MVT::v4i16, MVT::v8i16, MVT::v2i32,
----------------
DavidTruby wrote:
> sdesmalen wrote:
> > nit: is MVT::v2f16 missing or is this type widened?
> I believe v2f16 isn't a legal type here, so we don't want to do the custom lowering for it. We can just allow it to be handled as before.
Fair enough. Would it be good to at least add a test for it?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D101834/new/
https://reviews.llvm.org/D101834
More information about the llvm-commits
mailing list