[PATCH] D102498: [AArch64][SVE] Improve codegen for fixed length vector concat

[Bradley Smith via Phabricator via llvm-commits]

bsmith added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17694
 
+SDValue AArch64TargetLowering::LowerFixedLengthConcatVectorsToSVE(
+    SDValue Op, SelectionDAG &DAG) const {
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junparser wrote:
> Can we still use ConcatVector here and then lower it performConcatVectorsCombine or td file?
This is consistent with how all other fixed length operations are handled. The issue with trying to do this in tablegen, is that we'd have to add patterns for every single <= 2048-bit vector type, which is just going to cause an explosion of patterns.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102498/new/

https://reviews.llvm.org/D102498