[PATCH] D102498: [AArch64][SVE] Improve codegen for fixed length vector concat
Bradley Smith via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon May 17 03:44:38 PDT 2021
bsmith added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17694
+SDValue AArch64TargetLowering::LowerFixedLengthConcatVectorsToSVE(
+ SDValue Op, SelectionDAG &DAG) const {
----------------
junparser wrote:
> Can we still use ConcatVector here and then lower it performConcatVectorsCombine or td file?
This is consistent with how all other fixed length operations are handled. The issue with trying to do this in tablegen, is that we'd have to add patterns for every single <= 2048-bit vector type, which is just going to cause an explosion of patterns.
Repository:
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CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D102498/new/
https://reviews.llvm.org/D102498
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