[PATCH] D102498: [AArch64][SVE] Improve codegen for fixed length vector concat

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17702
+
+  assert(SrcVT == SrcOp2.getValueType());
+
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joechrisellis wrote:
> Can we add a message to the assertion?
I'd go the other way I just remove the assert.  By definition all the operands of `ISD::CONCAT_VECTORS` must have the same type so it's not really the job of this function to validate the DAG is not malformed. 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102498/new/

https://reviews.llvm.org/D102498