[PATCH] D102606: [RISCV] Fix operand order in fixed-length VM(OR|AND)NOT patterns

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck created this revision.
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Where the RVV specification writes `vs2, vs1`, our TableGen patterns use
`rs1, rs2`. These differences can easily cause confusion. The VMANDNOT
instruction performs `LHS && !RHS`, and similarly for VMORNOT.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D102606

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll

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