[PATCH] D102596: [PowerPC] only check the load instruction result number 0

[ChenZheng via Phabricator via llvm-commits]

shchenz created this revision.
shchenz added reviewers: nemanjai, jsji, PowerPC.
Herald added subscribers: kbarton, hiraditya.
shchenz requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

this patch:
1: generates more reverse memory load operations, because now the transformation only bases on load instruction result number 0.
2: fixes an exposed bug related to the reverse memory load location. Without the load location fix, the fixed case would be like:

  ; CHECK:       # %bb.0:
  ; CHECK-NEXT:    stxv 34, 0(3)
  ; CHECK-NEXT:    lxvd2x 34, 0, 3
  ; CHECK-NEXT:    blr


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D102596

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/vsx-shuffle-le-load.ll


Index: llvm/test/CodeGen/PowerPC/vsx-shuffle-le-load.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/vsx-shuffle-le-load.ll
+++ llvm/test/CodeGen/PowerPC/vsx-shuffle-le-load.ll
@@ -5,9 +5,9 @@
 define <2 x double> @loadChainHasUser(<2 x double>* %p1, <2 x double> %v2) {
 ; CHECK-LABEL: loadChainHasUser:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-NEXT:    stxv 34, 0(3)
-; CHECK-NEXT:    xxswapd 34, 0
+; CHECK-NEXT:    xxlor 34, 0, 0
 ; CHECK-NEXT:    blr
   %v1 = load <2 x double>, <2 x double>* %p1
   store <2 x double> %v2, <2 x double>* %p1, align 16
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -14627,12 +14627,15 @@
     return SDValue();
 
   if (LSBase->getOpcode() == ISD::LOAD) {
-    // If the load has more than one user except the shufflevector instruction,
-    // it is not profitable to replace the shufflevector with a reverse load.
-    if (!LSBase->hasOneUse())
-      return SDValue();
+    // If the load return value 0 has more than one user except the
+    // shufflevector instruction, it is not profitable to replace the
+    // shufflevector with a reverse load.
+    for (SDNode::use_iterator UI = LSBase->use_begin(), UE = LSBase->use_end();
+         UI != UE; ++UI)
+      if (UI.getUse().getResNo() == 0 && UI->getOpcode() != ISD::VECTOR_SHUFFLE)
+        return SDValue();
 
-    SDLoc dl(SVN);
+    SDLoc dl(LSBase);
     SDValue LoadOps[] = {LSBase->getChain(), LSBase->getBasePtr()};
     return DAG.getMemIntrinsicNode(
         PPCISD::LOAD_VEC_BE, dl, DAG.getVTList(VT, MVT::Other), LoadOps,


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