[llvm] f6584b8 - [PowerPC] add a testcase for reverse memory op; nfc

[Chen Zheng via llvm-commits]

Author: Chen Zheng
Date: 2021-05-17T03:29:14-04:00
New Revision: f6584b85c644fdbffd5e7617a68ceb3f8d140aec

URL: https://github.com/llvm/llvm-project/commit/f6584b85c644fdbffd5e7617a68ceb3f8d140aec
DIFF: https://github.com/llvm/llvm-project/commit/f6584b85c644fdbffd5e7617a68ceb3f8d140aec.diff

LOG: [PowerPC] add a testcase for reverse memory op; nfc

Added: 
    llvm/test/CodeGen/PowerPC/vsx-shuffle-le-load.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/CodeGen/PowerPC/vsx-shuffle-le-load.ll b/llvm/test/CodeGen/PowerPC/vsx-shuffle-le-load.ll
new file mode 100644
index 0000000000000..3057fdc16fba5
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/vsx-shuffle-le-load.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=+vsx \
+; RUN:   -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+
+define <2 x double> @loadChainHasUser(<2 x double>* %p1, <2 x double> %v2) {
+; CHECK-LABEL: loadChainHasUser:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    stxv 34, 0(3)
+; CHECK-NEXT:    xxswapd 34, 0
+; CHECK-NEXT:    blr
+  %v1 = load <2 x double>, <2 x double>* %p1
+  store <2 x double> %v2, <2 x double>* %p1, align 16
+  %v3 = shufflevector <2 x double> %v1, <2 x double> %v1, <2 x i32> < i32 1, i32 0>
+  ret <2 x double> %v3
+}