[PATCH] D101834: [llvm][sve] Lowering for VLS MLOAD/MSTORE

[Kerry McLaughlin via Phabricator via llvm-commits]

kmclaughlin added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17211-17214
+  auto Cmp = DAG.getNode(AArch64ISD::SETCC_MERGE_ZERO, DL, CmpVT,
+                         {Pg, Op1, Op2, DAG.getCondCode(ISD::SETNE)});
+
+  return Cmp;
----------------
nit: can you just use `return DAG.getNode(AArch64ISD::SETCC_MERGE_ZERO...` here instead?


================
Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h:231-232
+    // For fixed vectors, avoid scalarization if using SVE for them.
+    if (isa<FixedVectorType>(DataType) && !ST->useSVEForFixedLengthVectors())
+      return false; // Fall back to scalarization of masked operations.
+
----------------
nit: is it maybe worth merging this with the `if (!ST->hasSVE())` condition above?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D101834/new/

https://reviews.llvm.org/D101834