[PATCH] D101834: [llvm][sve] Lowering for VLS MLOAD/MSTORE

[Bradley Smith via Phabricator via llvm-commits]

bsmith added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17217
+
+// Convert all fixed length vector loads larger than NEON to masked_loads.
+SDValue AArch64TargetLowering::LowerFixedLengthVectorMLoadToSVE(
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Nit: Neon sized vectors come through here also


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll:2
+; RUN: llc -aarch64-sve-vector-bits-min=128  -asm-verbose=0 < %s | FileCheck %s -D#VBYTES=16  -check-prefix=NO_SVE
+; RUN: llc -aarch64-sve-vector-bits-min=256  -asm-verbose=0 < %s | FileCheck %s -D#VBYTES=32  -check-prefixes=CHECK,VBITS_GE_256
+; RUN: llc -aarch64-sve-vector-bits-min=384  -asm-verbose=0 < %s | FileCheck %s -D#VBYTES=32  -check-prefixes=CHECK,VBITS_GE_256
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Nit: VBITS_GE_256 is redundant (it's used in all the same places as CHECK), just use CHECK.


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll:29
+; CHECK: ptrue p[[P0:[0-9]+]].s, vl2
+; CHECK: fcmeq v[[P1:[0-9]+]].2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
+; CHECK-NEXT: cmpne p[[P2:[0-9]+]].s, p[[P0]]/z, z[[P1]].s, #0
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Why is -NEXT missing from all of the fcmeq lines?

I see now that the loads are missing from the CHECK lines, they should probably be in for completeness. (Same for loads tests)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101834/new/

https://reviews.llvm.org/D101834