[PATCH] D101938: [RISCV] Initial version of a demand based vsetvli insertion pass.

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added a comment.

Thanks @craig.topper. This is a great cleanup compared to our existing approach (which was actually very conservative).

Some higher level questions:

- I understand we still want a global cleanup after this pass, don't we?
- Would be this pass a good moment to try to optimise those cases where the AVL and SEW/LMUL are not changed and the instruction has explicit EEW. (Maybe we need to add some extra `TSFlag` for those)
  - For instance if we are under `SEW=64` `LMUL=2` and `AVL=%avl` a `PseudoVLE32` that switches to `SEW=32`, `LMUL=½`, `AVL=%avl` I understand it can skip the `vsetvli` as it will behave as expected.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D101938/new/

https://reviews.llvm.org/D101938