[PATCH] D101831: [AArch64][SVE] Add unpredicated vector BIC ISD node

[Bradley Smith via Phabricator via llvm-commits]

bsmith updated this revision to Diff 344832.
bsmith added a comment.

- Merge `SelectSVELogicalImmNot` with `SelectSVELogicalImm`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101831/new/

https://reviews.llvm.org/D101831

Files:
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-unpred-form.ll

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