[PATCH] D101831: [AArch64][SVE] Add unpredicated vector BIC ISD node

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:3221
+  if (auto CNode = dyn_cast<ConstantSDNode>(N)) {
+    uint64_t ImmVal = ~CNode->getZExtValue();
+    SDLoc DL(N);
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This looks to be the only difference to `SelectSVELogicalImm` so I wondered if it's better to extend  `SelectSVELogicalImm` with an `Invert` parameter?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101831/new/

https://reviews.llvm.org/D101831