[PATCH] D102096: [DAGCombiner] Fix DAG combine store elimination, different address space.

[Hendrik Greving via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
hgreving marked an inline comment as done.
Closed by commit rG762ac725bf97: [DAGCombiner] Fix DAG combine store elimination, different address space. (authored by hgreving).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102096/new/

https://reviews.llvm.org/D102096

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/X86/dagcombine-dead-store.ll


Index: llvm/test/CodeGen/X86/dagcombine-dead-store.ll
===================================================================
--- llvm/test/CodeGen/X86/dagcombine-dead-store.ll
+++ llvm/test/CodeGen/X86/dagcombine-dead-store.ll
@@ -6,12 +6,11 @@
 ; The test's 'same' and 'diff' notation depicts whether the pointer value is the same
 ; or different.
 
-; FIXME: DAG combine incorrectly eliminates store if pointer is of same value.
-
 define i32 @copy_fs_same() {
 ; CHECK-LABEL: copy_fs_same:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movl 1, %eax
+; CHECK-NEXT:    movl %eax, %fs:1
 ; CHECK-NEXT:    retl
 entry:
    %0 = load i32, i32* inttoptr (i64 1 to i32*), align 4
@@ -36,6 +35,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl %eax, 1
+; CHECK-NEXT:    movl %eax, %fs:1
 ; CHECK-NEXT:    retl
 entry:
   store i32 %v, i32* inttoptr (i64 1 to i32*), align 4
@@ -62,6 +62,7 @@
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; CHECK-NEXT:    movl %eax, 168(%ecx)
+; CHECK-NEXT:    movl %eax, %fs:168(%ecx)
 ; CHECK-NEXT:    retl
   %p = getelementptr i32, i32* %b, i64 42
   %pa = addrspacecast i32* %p to i32 addrspace(257)*
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -17916,6 +17916,7 @@
   if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
     if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
         ST->isUnindexed() && ST->isSimple() &&
+        Ld->getAddressSpace() == ST->getAddressSpace() &&
         // There can't be any side effects between the load and store, such as
         // a call or store.
         Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
@@ -17929,7 +17930,8 @@
     if (ST->isUnindexed() && ST->isSimple() &&
         ST1->isUnindexed() && ST1->isSimple()) {
       if (ST1->getBasePtr() == Ptr && ST1->getValue() == Value &&
-          ST->getMemoryVT() == ST1->getMemoryVT()) {
+          ST->getMemoryVT() == ST1->getMemoryVT() &&
+          ST->getAddressSpace() == ST1->getAddressSpace()) {
         // If this is a store followed by a store with the same value to the
         // same location, then the store is dead/noop.
         return Chain;
@@ -17940,7 +17942,8 @@
           // BaseIndexOffset and the code below requires knowing the size
           // of a vector, so bail out if MemoryVT is scalable.
           !ST->getMemoryVT().isScalableVector() &&
-          !ST1->getMemoryVT().isScalableVector()) {
+          !ST1->getMemoryVT().isScalableVector() &&
+          ST->getAddressSpace() == ST1->getAddressSpace()) {
         const BaseIndexOffset STBase = BaseIndexOffset::match(ST, DAG);
         const BaseIndexOffset ChainBase = BaseIndexOffset::match(ST1, DAG);
         unsigned STBitSize = ST->getMemoryVT().getFixedSizeInBits();


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