[PATCH] D102318: [TargetRegisterInfo] Speed up getAllocatableSet. NFCI.

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
foad added reviewers: arsenm, qcolombet, bsaleil.
Herald added subscribers: hiraditya, tpr.
foad requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.

MachineRegisterInfo caches the reserved register set that is computed by
by TargetRegisterInfo::getReservedRegs, so call into MRI to get the
reserved regs to avoid recomputing them.

In particular this speeds up AMDGPU's SIFormMemoryClauses pass because
AMDGPU has a particularly complicated reserved set that is expensive to
compute.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D102318

Files:
  llvm/lib/CodeGen/TargetRegisterInfo.cpp


Index: llvm/lib/CodeGen/TargetRegisterInfo.cpp
===================================================================
--- llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -267,8 +267,9 @@
   }
 
   // Mask out the reserved registers
-  BitVector Reserved = getReservedRegs(MF);
-  Allocatable &= Reserved.flip();
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
+  const BitVector &Reserved = MRI.getReservedRegs();
+  Allocatable.reset(Reserved);
 
   return Allocatable;
 }


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