[PATCH] D102096: [DAGCombiner] Fix DAG combine store elimination, different address space.

[Hendrik Greving via Phabricator via llvm-commits]

hgreving updated this revision to Diff 344066.
hgreving marked an inline comment as done.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102096/new/

https://reviews.llvm.org/D102096

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/X86/dagcombine-dead-store.ll


Index: llvm/test/CodeGen/X86/dagcombine-dead-store.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/dagcombine-dead-store.ll
@@ -0,0 +1,45 @@
+; RUN: llc < %s -mtriple=i686-pc-linux | FileCheck %s
+
+; Checks that the stores aren't eliminated by the DAG combiner, because the address
+; spaces are different. In X86, we're checking this for two non-zero address spaces,
+; one for :fs and one for :gs.
+
+; CHECK-LABEL: copy_fs_same:
+; CHECK: movl 1, %eax
+; CHECK-NEXT: movl %eax, %fs:1
+define i32 @copy_fs_same() {
+entry:
+   %0 = load i32, i32* inttoptr (i64 1 to i32*), align 4
+  store i32 %0, i32 addrspace(257)* inttoptr (i64 1 to i32 addrspace(257)*), align 4
+  ret i32 %0
+}
+
+; CHECK-LABEL: copy_fs_diff:
+; CHECK: movl 1, %eax
+; CHECK-NEXT: movl %eax, %fs:2
+define i32 @copy_fs_diff() {
+entry:
+   %0 = load i32, i32* inttoptr (i64 1 to i32*), align 4
+  store i32 %0, i32 addrspace(257)* inttoptr (i64 2 to i32 addrspace(257)*), align 4
+  ret i32 %0
+}
+
+; CHECK-LABEL: copy_gs_same:
+; CHECK: movl 1, %eax
+; CHECK-NEXT: movl %eax, %gs:1
+define i32 @copy_gs_same() {
+entry:
+   %0 = load i32, i32* inttoptr (i64 1 to i32*), align 4
+  store i32 %0, i32 addrspace(256)* inttoptr (i64 1 to i32 addrspace(256)*), align 4
+  ret i32 %0
+}
+
+; CHECK-LABEL: copy_gs_diff:
+; CHECK: movl 1, %eax
+; CHECK-NEXT: movl %eax, %gs:2
+define i32 @copy_gs_diff() {
+entry:
+   %0 = load i32, i32* inttoptr (i64 1 to i32*), align 4
+  store i32 %0, i32 addrspace(256)* inttoptr (i64 2 to i32 addrspace(256)*), align 4
+  ret i32 %0
+}
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -17916,6 +17916,8 @@
   if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
     if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
         ST->isUnindexed() && ST->isSimple() &&
+        Ld->getPointerInfo().getAddrSpace() ==
+            ST->getPointerInfo().getAddrSpace() &&
         // There can't be any side effects between the load and store, such as
         // a call or store.
         Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {


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