[PATCH] D101938: [RISCV] Initial version of a demand based vsetvli insertion pass.
Hsiangkai Wang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu May 6 21:28:17 PDT 2021
HsiangKai added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:150
+ if (VLOp.isImm()) {
+ int64_t Imm = VLOp.getImm();
+
----------------
craig.topper wrote:
> HsiangKai wrote:
> > Should we check the range of immediate? vsetivli only has 5-bits immediate field.
> I can assert it. It should have been checked by SelectionDAG when the instruction was created.
Got it. That's fine without the assertion.
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https://reviews.llvm.org/D101938/new/
https://reviews.llvm.org/D101938
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