[PATCH] D101938: [RISCV] Initial version of a demand based vsetvli insertion pass.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: evandro, frasercrmck, HsiangKai, arcbbb, khchen, rogfer01.
Herald added subscribers: StephenFan, vkmr, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, arphaman, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, mgorny.
craig.topper requested review of this revision.
Herald added a subscriber: MaskRay.
Herald added a project: LLVM.

This patch adds a new pass to conservativley insert vsetvli's.
This replaces the current approach of aggressively adding them
and then trying to remove unneeded.

I've removed the custom inserter and implicit uses of vl/vtype
from the pseudo instructions. The implicit uses will be added
when the vsetvli instruction is inserted.

I've placed this pass after the SSA optimizations but while we
are still in SSE form. I'm considering pushing it later to after
the machine scheduler, but that affects more tests and requires
live intervals to be handled. Moving it after the scheduler may
allow us to add heuristics to the scheduler to group same vtype
and vsetvli operations together.

Other goals for this are to enable more intelligent selection of
vtype for mask instructions like vmand/vmor/vmxor, etc which
don't use SEW. More intelligent vtype selection for vmv.x.s which
doesn't use LMUL. If we are able to see the previous vtypes we can
avoid inserting a vsetvli for these instructions in some cases. This
is hard to do in the current design since we can't track the users
of a vsetvli when we are trying to see if it is unneeded.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101938

Files:
  llvm/lib/Target/RISCV/CMakeLists.txt
  llvm/lib/Target/RISCV/RISCV.h
  llvm/lib/Target/RISCV/RISCVCleanupVSETVLI.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir
  llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll
  llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
  llvm/test/CodeGen/RISCV/rvv/cleanup-vsetivli.mir
  llvm/test/CodeGen/RISCV/rvv/cleanup-vsetvli.mir
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
  llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
  llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
  llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir

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