[PATCH] D100788: [SystemZ] Support i128 inline asm operands

Ulrich Weigand via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed May 5 04:35:46 PDT 2021


uweigand added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:8568
+          const TargetRegisterClass *RC = nullptr;
+          if (RegVT == MVT::Untyped) {
+            const MachineFunction &MF = DAG.getMachineFunction();
----------------
jonpa wrote:
> uweigand wrote:
> > Instead of recomputing the RC here, can't we get it from the flag word of the matching operand, e.g. using `hasRegClassConstraint(OpFlag, RCID)`?  This would match the way we get the number of registers from the flag word instead of recomputing it as well.
> No - the matching operand may be a specific physreg in which case there is no register class specified (e.g. SystemZ/asm-17.ll).
> 
Hmm, maybe I'm confused but I thought in those cases, we'd still get the RC for that physreg installed into the flags.  Isnt't that exactly what the code in AddInlineAsmOperands does:

```
    const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
    Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());

```
(Regs.front() should have been set up to the physreg if there's one.)



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  https://reviews.llvm.org/D100788/new/

https://reviews.llvm.org/D100788



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