[PATCH] D101820: [AArch64][SVE] Extend svdup->insertelement instcombine pattern to support ...

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:392
+  // this DUP are other DUPs that overwrite every vector element except for
+  // one. If this condition is not true, bail out.
+  if (PTruePattern != AArch64SVEPredPattern::vl1) {
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Instead of checking for this specific pattern, can we leverage simplifyDemandedVectorEltsIntrinsic?  I guess that doesn't currently work with scalable vectors, though...


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  https://reviews.llvm.org/D101820/new/

https://reviews.llvm.org/D101820