[PATCH] D101828: [AArch64][SVE] Better utilisation of unpredicated forms of remaining intrinsics

Bradley Smith via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue May 4 05:08:29 PDT 2021


bsmith created this revision.
bsmith added reviewers: paulwalker-arm, peterwaller-arm, joechrisellis, sdesmalen.
Herald added subscribers: psnobl, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
bsmith requested review of this revision.
Herald added a project: LLVM.
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When using predicated intrinsics, if the predicate used is all lanes active,
use an unpredicated form of the instruction, additionally this allows for
better use of immediate forms.

This only includes instructions where the unpredicated/predicated forms
matched in such a way that instruction selection would not introduce extra
ptrue instructions. This allows us to convert the intrinsics directly to
architecture independent ISD nodes.

Depends on D101062 <https://reviews.llvm.org/D101062>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101828

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-unpred-form.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-int-arith-imm.ll

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