[PATCH] D100527: [AArch64][SVE] More unpredicated ld1/st1 patterns for reg+reg addressing modes

[Eli Friedman via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8a40bf6d210f: [AArch64][SVE] More unpredicated ld1/st1 patterns for reg+reg addressing modes (authored by efriedma).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100527/new/

https://reviews.llvm.org/D100527

Files:
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
  llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-reg.ll
  llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-reg.ll

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