[PATCH] D101769: [LegalizeIntegerTypes] Promote EXTEND_VECTOR_INREG operands
Fraser Cormack via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon May 3 10:35:04 PDT 2021
frasercrmck created this revision.
frasercrmck added reviewers: craig.topper, RKSimon.
Herald added subscribers: luismarques, apazos, sameer.abuasal, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
frasercrmck requested review of this revision.
Herald added subscribers: llvm-commits, MaskRay.
Herald added a project: LLVM.
This patch adds support for the TypePromoteInteger action on the
operands of the various *_EXTEND_VECTOR_INREG nodes.
The attached test case covers the situation where the operand of
v128i32 = any_extend_vector_inreg v256i16
is promoted to
v128i32 = any_extend_vector_inreg v256i32
The shuffle is eventually scalarized so the output is unwieldy and the
test isn't particularly quick to compile.
In terms of the ideal RISC-V codegen, we may want to add v256i16 to the
list of MVT types, at which point we'd stop scalarizing the shuffle but
lose our only test case.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D101769
Files:
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/test/CodeGen/RISCV/rvv/any-extend-vector-inreg.ll
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