[PATCH] D101414: [AMDGPU] Disable the scalar IR, SDWA and load store vectorizer passes at -O1

[Baptiste Saleil via Phabricator via llvm-commits]

bsaleil marked 2 inline comments as done.
bsaleil added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp:904
 
-    if (EnableScalarIRPasses)
+    if (EnableScalarIRPasses && TM.getOptLevel() > CodeGenOpt::Less)
       addStraightLineScalarOptimizationPasses();
----------------
foad wrote:
> arsenm wrote:
> > This seems like a weird interaction between flags. Maybe this should check if EnableScalarIRPasses was explicitly used? Or maybe we can just drop EnableScalarIRPasses entirely
> I agree that `EnableScalarIRPasses.getNumOccurrences() ? EnableScalarIRPasses : TM.getOptLevel() > CodeGenOpt::Less` would be saner.
You're right, that makes a lot more sense. I just updated the patch and added a RUN line in the test case to ensure the passes are run for -O1 when we explicitly provide the flags.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D101414/new/

https://reviews.llvm.org/D101414