[PATCH] D101414: [AMDGPU] Disable the scalar IR, SDWA and load store vectorizer passes at -O1

[Baptiste Saleil via Phabricator via llvm-commits]

bsaleil updated this revision to Diff 342017.
bsaleil added a comment.

Enable the passes only from -O2 or when explicitly enabled with flags. Also update the test case to ensure the passes are run for -O1 when explicitly enabled.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101414/new/

https://reviews.llvm.org/D101414

Files:
  llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  llvm/test/CodeGen/AMDGPU/llc-pipeline.ll

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