[PATCH] D100816: [AArch64][SVE] Lower index_vector to step_vector

[JunMa via Phabricator via llvm-commits]

junparser added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:13654-13664
+  if (isa<ConstantSDNode>(Op2)) {
+    // Lower index_vector(base, step) to step_vector(step) + splat(base).
+    Op2 = DAG.getConstant((cast<ConstantSDNode>(Op2))
+                              ->getAPIntValue()
+                              .sextOrSelf(ScalarTy.getSizeInBits()),
+                          DL, ScalarTy);
+    SDValue StepVector =
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paulwalker-arm wrote:
> With your previous DAGCombine patches in mind I figured I'd take this patch for a test drive and I believe there's no longer need for this specialisation because the generic block (i.e. the else case) lowers to the expected output (or at least running this patches version of sve-intrinsics-index.ll reports a pass).
Yes, previous DAGCombine patches can handle this. Then I'll remove the if part.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100816/new/

https://reviews.llvm.org/D100816