[PATCH] D100816: [AArch64][SVE] Lower index_vector to step_vector

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

Assuming you agree I think you can just delete a bit of code and then the patch is good to go.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:13654-13664
+  if (isa<ConstantSDNode>(Op2)) {
+    // Lower index_vector(base, step) to step_vector(step) + splat(base).
+    Op2 = DAG.getConstant((cast<ConstantSDNode>(Op2))
+                              ->getAPIntValue()
+                              .sextOrSelf(ScalarTy.getSizeInBits()),
+                          DL, ScalarTy);
+    SDValue StepVector =
----------------
With your previous DAGCombine patches in mind I figured I'd take this patch for a test drive and I believe there's no longer need for this specialisation because the generic block (i.e. the else case) lowers to the expected output (or at least running this patches version of sve-intrinsics-index.ll reports a pass).


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:15464-15466
+static SDValue performStepVectorCombine(SDNode *N,
+                                        TargetLowering::DAGCombinerInfo &DCI,
+                                        SelectionDAG &DAG) {
----------------
FYI: I imagine we're only a few isel patterns away from not need this, but there's no need to hold up this patch for it.


Repository:
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  https://reviews.llvm.org/D100816/new/

https://reviews.llvm.org/D100816