[PATCH] D101580: [AArch64] Fix scalar imm variants of SIMD shift left instructions

[Andrew Savonichev via Phabricator via llvm-commits]

asavonic created this revision.
asavonic added reviewers: dmgreen, SjoerdMeijer, t.p.northover, fhahn, Amanieu.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls.
asavonic requested review of this revision.
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This issue was reported in PR50057: Cannot select:
t10: i64 = AArch64ISD::VSHL t2, Constant:i32<2>

Shift intrinsics (llvm.aarch64.neon.ushl.i64 and sshl) with a constant
shift operand are lowered into AArch64ISD::VSHL in tryCombineShiftImm.
VSHL has i64 and v1i64 patterns for a right shift, but only v1i64 for
a left shift.

This patch adds the missing i64 pattern for AArch64ISD::VSHL, and LIT
tests to cover scalar variants (i64 and v1i64) of all shift
intrinsics (only ushl and sshl cases fail without the patch, others
were just not covered).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101580

Files:
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/test/CodeGen/AArch64/arm64-vshift.ll

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